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CAT1026, CAT1027
Dual Voltage Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM FEATURES
s Precision VCC power supply voltage monitor s Low power CMOS technology s 16-Byte page write buffer
H
GEN FR ALO
EE
LE
A D F R E ETM
-- 5V, 3.3 V and 3 V systems -- Five threshold voltage options
s Additional voltage monitoring
s Built-in inadvertent write protection s 1,000,000 Program/Erase cycles s Manual reset capability s 100 year data retention s 8-pin DIP, SOIC, TSSOP, MSOP or TDFN
-- Externally adjustable down to 1.25 V
s Watchdog timer (CAT1027 only) s Active high or low reset
-- Valid reset guaranteed to VCC = 1 V
s 400 kHz I C bus s 2.7 V to 5.5 V operation
2
(3 x 4.9 mm & 3 x 3 mm foot-print) packages -- TDFN max height is 0.8mm
s Industrial and extended temperature ranges
DESCRIPTION
The CAT1026 and CAT1027 are complete memory and supervisory solutions for microcontroller-based systems. A 2k-bit serial EEPROM memory and a system power supervisor with brown-out protection are integrated together in low power CMOS technology. Memory interface is via a 400kHz I2C bus. The CAT1026 and CAT1027 provide a precision VCC sense circuit with five reset threshold voltage options that support 5V, 3.3V and 3V systems. The power supply monitor and reset circuit protects memory and systems controllers during power up/down and against brownout conditions. If power supply voltages are out of tolerance reset signals become active preventing the system microcontroller, ASIC, or peripherals from operating. used as an input for push-button manual reset capability. The CAT1026 and CAT1027 provide an auxiliary voltage sensor input, VSENSE, which is used to monitor a second system supply. The auxiliary high impedance comparator drives the open drain output, VLOW, whenever the sense voltage is below 1.25V threshold. The CAT1027 is designed with a 1.6 second watchdog timer circuit that resets a system to a known state if software or a hardware glitch halts or "hangs" the system. The CAT1027 features a watchdog timer interrupt input, WDI.
The on-chip 2k-bit EEPROM memory features a 16-byte page. In addition, hardware data protection is provided by a VCC sense circuit that prevents writes to memory whenever VCC falls below the reset threshold or until VCC reaches the The CAT1026 features two open drain reset outputs: reset threshold during power up. one (RESET) drives high and the other (RESET) drives Available packages include 8-pin DIP and surface mount, low whenever VCC falls below the threshold. Reset 8-pin SO, 8-pin TSSOP, 8-pin TDFN and 8-pin MSOP outputs become inactive typically 200 ms after the packages. The TDFN package thickness is 0.8mm supply voltage exceeds the reset threshold value. With maximum. TDFN footprint options are 3x3mm or 3x4.9mm both active high and low reset signals, interface to (MSOP pad layout). microcontrollers and other ICs is simple. CAT1027 has only a RESET output. In addition, the RESET pin can be
(c) 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
Doc No. 3010, Rev. H
CAT1026, CAT1027
BLOCK DIAGRAM
EXTERNAL LOAD DOUT ACK VCC VSS WORD ADDRESS BUFFERS COLUMN DECODERS SENSE AMPS SHIFT REGISTERS
RESET Threshold Options Part Dash Minimum Maximum Number Threshold Threshold
-45 -42 -30 -28 -25 4.50 4.25 3.00 2.85 2.55 4.75 4.50 3.15 3.00 2.70
SDA
START/STOP LOGIC 2kbit EEPROM
XDEC CONTROL LOGIC
DATA IN STORAGE VCC Monitor VCC
HIGH VOLTAGE/ TIMING CONTROL STATE COUNTERS
SCL
+ VREF
RESET Controller
WDI (CAT1027)
SLAVE ADDRESS COMPARATORS
Auxiliary Voltage Monitor VSENSE VREF
RESET (CAT1026) VLOW
RESET
+ -
PIN CONFIGURATION
DIP Package (P, L) SOIC Package (S, V) TSSOP Package (U, Y) MSOP Package (R, Z)
VLOW 1 RESET 2 VSENSE 3 VSS 4 8 VCC 7 RESET 6 SCL 5 SDA
(Bottom View) TDFN Package: 3mm x 4.9mm 0.8mm maximum height - (RD2, ZD2)
VCC RESET SCL SDA
8 7 1 2
(Bottom View) TDFN Package: 3mm x 3mm 0.8mm maximum height - (RD4, ZD4)
VCC RESET SCL SDA
8 7 1 2
VLOW RESET VSENSE VSS
VLOW RESET VSENSE VSS
CAT1026
CAT1026
6 5
3 4
CAT1026
6 5
3 4
VLOW 1 RESET 2 VSENSE 3 VSS 4
8 VCC CAT1027 7 WDI 6 SCL 5 SDA
VCC WDI SCL SDA
8 7
1 2
VLOW RESET VSENSE VSS
VCC WDI SCL SDA
8 7
1 2
VLOW RESET VSENSE VSS
CAT1027
6 5
CAT1027
6 5
3 4
3 4
Doc. No. 3010, Rev. H
2
CAT1026, CAT1027
PIN DESCRIPTION
RESET/RESET RESET: RESET OUTPUTS RESET (RESET CAT1026 Only) These are open drain pins and RESET can be used as a manual reset trigger input. By forcing a reset condition on the pin the device will initiate and maintain a reset condition. The RESET pin must be connected through a pull-down resistor, and the RESET pin must be connected through a pull-up resistor. SDA: SERIAL DATA ADDRESS The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. SCL: SERIAL CLOCK Serial clock input. VSENSE: AUXILIARY VOLTAGE MONITOR INPUT The VSENSE input is a second voltage monitor which is compared against CAT1026 and CAT1027 internal reference voltage of 1.25V typically. Whenever the input voltage is lower than 1.25V, the open drain VLOW output will be driven low. An external resistor divider is used to set the voltage level to be sensed. Connect VSENSE to VCC if unused. VLOW: AUXILIARY VOLTAGE MONITOR OUTPUT This open drain output goes low when VSENSE is less than 1.25V and goes high when VSENSE exceeds the reference voltage. WDI (CAT1027 Only): WATCHDOG TIMER INTERRUPT Watchdog Timer Interrupt Input is used to reset the watchdog timer. If a transition from high to low or low to high does not occur every 1.6 seconds, the RESET outputs will be driven active.
PIN FUNCTIONS
Pin Name
RESET VSS SDA SCL RESET VCC VSENSE VLOW WDI
OPERATING TEMPERATURE RANGE
Industrial Extended -40C to 85C -40C to 125C
Function
Active Low Reset Input/Output Ground Serial Data/Address Clock Input Active High Reset Output (CAT1026 only) Power Supply Auxiliary Voltage Monitor Input Auxiliary Voltage Monitor Output Watchdog Timer Interrupt (CAT1027 only)
CAT10XX FAMILY OVERVIEW
Device Manual Reset Input Pin Watchdog Watchdog Monitor Pin SDA SDA WDI Write Protection Pin Independent Auxiliary Voltage Sense RESET: Active High and LOW EEPROM
CAT1021 CAT1022 CAT1023 CAT1024 CAT1025 CAT1026 CAT1027
2k 2k 2k 2k 2k 2k
WDI
2k
For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163 data sheets.
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Doc No. 3010, Rev. H
CAT1026, CAT1027
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................. -55C to +125C Storage Temperature ....................... -65C to +150C Voltage on any Pin with Respect to Ground(1) ........... -2.0 V to VCC + 2.0 V VCC with Respect to Ground ............ -2.0 V to + 7.0 V Package Power Dissipation Capability (TA = 25C) .................................. 1.0 W
Lead Soldering Temperature (10 seconds) ...... 300C Output Short Circuit Current(2) ........................ 100 mA
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time.
DC OPERATING CHARACTERISTICS
VCC = 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified.
Symbol ILI ILO ICC1 ICC2 ISB VIL(1) VIH
(1)
Parameter Input Leakage Current Output Leakage Current Power Supply Current (Write) Power Supply Current (Read) Standby Current Input Low Voltage Input High Voltage Output Low Voltage (SDA, RESET , VLOW) Output High Voltage (RESET)
Test Conditions VIN = GND to Vcc VIN = GND to Vcc fSCL = 400 kHz VCC = 5.5 V fSCL = 400 kHz VCC = 5.5 V Vcc = 5.5V CAT1026 VIN = GND or Vcc CAT1027
Min -2 -10
Typ
Max 10 10 3 1 50 60
Units A A mA mA A V V V V
-0.5 0.7 x Vcc IOL = 3 mA VCC = 2.7 V IOH = -0.4 mA VCC = 2.7 V CAT102x-45 (VCC = 5.0 V) CAT102x-42 (VCC = 5.0 V) Vcc 0.75 4.50 4.25 3.00 2.85 2.55 1.00 15 1.2 1.25
0.3 x Vcc Vcc + 0.5 0.4
VOL VOH
4.75 4.50 3.15 3.00 2.70 V mV 1.3 V V
VTH
Reset Threshold (VCC Monitor)
CAT102x-30 (VCC = 3.3 V) CAT102x-28 (VCC = 3.3 V) CAT102x-25 (VCC = 3.0 V)
VRVALID VRT(2) VREF
Reset Output Valid VCC Voltage Reset Threshold Hysteresis Auxiliary Voltage Monitor Threshold
Notes: 1. VIL min and VIH max are reference values only and are not tested. 2. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
Doc. No. 3010, Rev. H
4
CAT1026, CAT1027
CAPACITANCE
TA = 25C, f = 1.0 MHz, VCC = 5V Symbol COUT
(1)
Test Output Capacitance Input Capacitance
Test Conditions VOUT = 0 V VIN = 0 V
Max 8 6
Units pF pF
CIN(1)
AC CHARACTERISTICS
VCC = 2.7 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle(2)
Symbol fSCL tSP tLOW tHIGH tR(1) tF(1) tHD;STA tSU;STA tHD;DAT tSU;DAT tSU;STO tAA tDH tBUF(1) tWC(3) Parameter Clock Frequency Input Filter Spike Suppression (SDA, SCL) Clock Low Period Clock High Period SDA and SCL Rise Time SDA and SCL Fall Time Start Condition Hold Time Start Condition Setup Time (for a Repeated Start) Data Input Hold Time Data Input Setup Time Stop Condition Setup Time SCL Low to Data Out Valid Data Out Hold Time Time the Bus must be Free Before a New Transmission Can Start Write Cycle Time (Byte or Page) 50 1.3 5 0.6 0.6 0 100 0.6 900 1.3 0.6 300 300 Min Max 400 100 Units kHz ns s s ns ns s s ns ns s ns ns s ms
Notes: 1. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. 2. Test Conditions according to "AC Test Conditions" table. 3. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
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Doc No. 3010, Rev. H
CAT1026, CAT1027
VOLTAGE MONITOR AND RESET CIRCUIT AC CHARACTERISTICS
Symbol tPURST tRPD1 tGLITCH tWD tRPD2 Parameter Reset Timeout VTH to RESET Output Delay VCC Glitch Reject Pulse Width Watchdog Timeout VSENSE to VLOW Delay Test Conditions Note 2 Note 3 Note 4, 6 Note 1 Note 5 1.0 1.6 Min 130 Typ 200 Max 270 5 30 2.1 5 Units ms s ns sec s
POWER-UP TIMING6,7
Symbol tPUR tPUW Parameter Power-Up to Read Operation Power-Up to Write Operation Test Conditions Min Typ Max 270 270 Units ms ms
AC TEST CONDITIONS
Parameter Input Pulse Voltages Input Rise and Fall Times Input Reference Voltages Output Reference Voltages Output Load Conditions 0.2 VCC to 0.8 VCC 10 ns 0.3 VCC , 0.7 VCC 0.5 VCC Current Source: IOL = 3 mA; CL = 100 pF
RELIABILITY CHARACTERISTICS
Symbol NEND
(6)
Parameter Endurance Data Retention ESD Susceptibility Latch-Up
Reference Test Method
Min
Max
Units Cycles/Byte Years Volts mA
MIL-STD-883, Test Method 1033 1,000,000 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 100 2000 100
TDR(6) VZAP(6) ILTH(6)(8)
Notes: 1. Test Conditions according to "AC Test Conditions" table. 2. Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to "AC Test Conditions" Table. 3. Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to "AC Test Conditions" Table. 4. VCC Glitch Reference Voltage = VTHmin; Based on characterization data. 5. 0 < VSENSE VCC, VLOW Output Reference Voltage and Load according to "AC Test Conditions" Table. 6. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. 7. tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated. 8. Latch-up protection is provided for stresses up to 100mA on input and output pins from -1 V to VCC + 1 V.
Doc. No. 3010, Rev. H
6
CAT1026, CAT1027
DEVICE OPERATION
Reset Controller Description The CAT1026 and CAT1027 precision RESET controllers ensure correct system operation during brownout and power up/down conditions. They are configured with open drain RESET outputs. During power-up, the RESET outputs remain active until VCC reaches the VTH threshold and will continue driving the outputs for approximately 200 ms (tPURST) after reaching VTH. After the tPURST timeout interval, the device will cease to drive the reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/down resistors. During power-down, the RESET outputs will be active when VCC falls below VTH. The RESET output will be valid so long as VCC is >1.0 V (VRVALID). The device is designed to ignore the fast negative going VCC transient pulses (glitches). Reset output timing is shown in Figure 1. Manual Reset Capability The RESET pin can operate as reset output and manual reset input. The input is edge triggered; that is, the RESET input will initiate a reset timeout after detecting a high to low transition. When RESET I/O is driven to the active state, the 200 msec timer will begin to time the reset interval. If external reset is shorter than 200 ms, Reset outputs will remain active at least 200 ms. Monitoring Two Voltages The CAT1026 and CAT1027 feature a second voltage sensor, VSENSE, which drives the open drain VLOW output low whenever the input voltage is below 1.25 V. The auxiliary voltage monitor timing is shown in Figure 2. By using an external resistor divider the sense circuitry can be set to monitor a second supply in the system. The circuit shown in Figure 3 provides an externally adjustable threshold voltage, VTH_ADJ to monitor the auxiliary voltage. The low leakage current at VSENSE allows the use of large value resistors, to reduce the system power consumption. The VLOW output can be externally connected to the RESET output to generate a reset condition when either of the supplies is invalid. In other applications, VLOW signal can be used to interrupt the system controller for an impending power failure notification. Data Protection The CAT1026 and CAT1027 devices have been designed to solve many of the data corruption issues that have long been associated with serial EEPROMs. Data corruption occurs when incorrect data is stored in a memory location which is assumed to hold correct data. Whenever the device is in a Reset condition, the embedded EEPROM is disabled for all operations, including write operations. If the Reset output(s) are active, in progress communications to the EEPROM are aborted and no new communications are allowed. In this condition an internal write cycle to the memory can not be started, but an in progress internal non-volatile memory write cycle can not be aborted. An internal write cycle initiated before the Reset condition can be successfully finished if there is enough time (5ms) before VCC reaches the minimum value of 2 V. In addition, to avoid data corruption due to the loss of power supply voltage during the memory internal write operation, the system controller should monitor the unregulated DC power. Using the second voltage sensor, VSENSE, to monitor an unregulated power supply, the CAT1026 and CAT1027 signals an impending power failure by setting VLOW low. Watchdog Timer The Watchdog Timer provides an independent protection for microcontrollers. During a system failure, the CAT1027 device will provide a reset signal after a time-out interval of 1.6 seconds for a lack of activity. CAT1027 is designed with the Watchdog timer feature on the WDI pin. If WDI does not toggle within 1.6 second intervals, the reset condition will be generated on reset output. The watchdog timer is cleared by any transition on monitored line. As long as reset signal is asserted, the watchdog timer will not count and will stay cleared.
7
Doc No. 3010, Rev. H
CAT1026, CAT1027
t
Figure 1. RESET Output Timing
GLITCH
VTH VRVALID VCC t PURST t RPD1 t PURST t RPD1
RESET
RESET
Figure 2. Auxiliary Voltage Monitor Timing
VREF VSENSE tRPD2 tRPD2 tRPD2 tRPD2
VLOW
Figure 3. Auxiliary Voltage Monitor
VCC
VAUX Externally adjustable threshold R1 VTH-ADJ
CAT1026/27
VLOW VSENSE Power Fail Interrupt
R2
VTH-ADJ = VREF x
R + R2 R1 + R 2 = 1.25V x 1 R2 R2
Doc. No. 3010, Rev. H
8
CAT1026, CAT1027
EMBEDDED EEPROM OPERATION
The CAT1026 and CAT1027 feature a 2kbit embedded serial EEPROM that supports the I 2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. I2C Bus Protocol The features of the I2C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT1026 and CAT1027 monitor the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are programmable in metal and the default is 1010. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT1026 and CAT1027 monitor the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT1026 and CAT1027 then perform a Read or Write operation depending on the R/W bit.
Figure 4. Bus Timing
tF tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO tHIGH tLOW tR
SDA IN tAA SDA OUT tDH tBUF
Figure 5. Write Cycle Timing
SCL
SDA
8TH BIT BYTE n
ACK tWR STOP CONDITION START CONDITION ADDRESS
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Doc No. 3010, Rev. H
CAT1026, CAT1027
ACKNOWLEDGE
After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT1026 and CAT1027 respond with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the CAT1026 and CAT1027 begin a READ mode it transmits 8 bits of data, releases the SDA line and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT1026 and CAT1027 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. Figure 6. Start/Stop Timing
WRITE OPERATIONS
Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends a 8-bit address that is to be written into the address pointers of the device. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT1026 and CAT1027 acknowledge once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to non-volatile memory. While the cycle is in progress, the device will not respond to any request from the Master device.
SDA
SCL START BIT STOP BIT
Figure 7. Acknowledge Timing
SCL FROM MASTER 1 8 9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
Figure 8. Slave Address Bits Default Configuration CAT
1 0 1 0 0 0 0 R/W
Doc. No. 3010, Rev. H
10
CAT1026, CAT1027
Page Write The CAT1026 and CAT1027 write up to 16 bytes of data in a single write cycle, by using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted, the CAT1026 and CAT1027 will respond with an acknowledge and internally increment the lower order address bits by one. The high order bits remain unchanged. If the Master transmits more than 16 bytes before sending the STOP condition, the address counter `wraps around,' and previously transmitted data will be overwritten. When all 16 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT1026 and CAT1027 in a single write cycle.
Figure 9. Byte Write Timing
S T A R T S A C K A C K A C K
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
BYTE ADDRESS
DATA
S T O P P
Figure 10. Page Write Timing
BUS ACTIVITY: MASTER SDA LINE
S T A R T S
SLAVE ADDRESS
BYTE ADDRESS (n)
DATA n
DATA n+1
S T DATA n+15 O P P
A C K
A C K
A C K
A C K
A C K
11
Doc No. 3010, Rev. H
CAT1026, CAT1027
Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write opration, the CAT1026 and CAT1027 initiate the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the device is still busy with the write operation, no ACK will be returned. If a write operation has completed, an ACK will be returned and the host can then proceed with the next read or write operation. Figure 11. Immediate Address Read Timing Read Operations The READ operation for the CAT1026 and CAT1027 is initiated in the same manner as the write operation with one exception, the R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ.
BUS ACTIVITY: MASTER SDA LINE
S T A R T S
SLAVE ADDRESS
S T O P P A C K DATA N O A C K
SCL
8
9
SDA
8TH BIT DATA OUT NO ACK STOP
Doc. No. 3010, Rev. H
12
CAT1026, CAT1027
Immediate/Current Address Read The CAT1026 and CAT1027 address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N + 1. For N = E = 255, the counter will wrap around to zero and continue to clock out valid data. After the CAT1026 and CAT1027 receive a slave address (with the R/W bit set t o one), an acknowledge is issued, and the requested 8-bit byte is transmitted. The master device does not send an acknowledge, but will generate a STOP condition. Selective/Random Read Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a `dummy' write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After the CAT1026 and CAT1027 acknowledge, the Master device sends the START condition and the slave address again, this time with the R/W bit set to one. The CAT1026 and CAT1027 then respond with an acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT1026 and CAT1027 send the inital 8-bit byte requested, the Master responds with an acknowledge which tells the device it requires more data. The CAT1026 and CAT1027 will continue to output an 8-bit byte for each acknowledge, thus sending the STOP condition. The data being transmitted from the CAT1026 and CAT1027 is sent sequentially with the data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT1026 and CAT1027 address bits so that the entire memory array can be read during one operation.
Figure 12. Selective Read Timing
BUS ACTIVITY: MASTER SDA LINE
S T A R T S
SLAVE ADDRESS
BYTE ADDRESS (n)
S T A R T S
SLAVE ADDRESS
S T O P P A C K DATA n N O A C K
A C K
A C K
Figure 13. Sequential Read Timing
S T O P P A C K A C K A C K A C K N O A C K
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
13
Doc No. 3010, Rev. H
CAT1026, CAT1027
PACKAGE OUTLINES TDFN 3X4.9 PACKAGE (RD2)
8 5 A B 5 8
4.90 + 0.10 (5)
3.00 + 0.15
2.00 + 0.15
0.10
0.15 0.20
0.60 + 0.10 (8X)
2x
PIN 1 ID
d 0.15 c 1 PIN 1 INDEX AREA 3.00 + 0.10 (S) 4
2x d 0.15 c
4 0.30 + 0.05 (8X) 8x j 0.10m C A B
1 0.65 TYP. (6x) 1.95 REF. (2x) 0.75 + 0.05
f 0.10 c 8x d 0.08 c C 0.20 REF.
NOTE: 1. ALL DIMENSION ARE IN mm. ANGLES IN DEGREES. 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. COPLANARITY SHALL NOT EXCEED 0.08mm. 3. WARPAGE SHALL NOT EXCEED 0.10mm. 4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC(S). 5. REFER TO JEDEC MO-229, FOOTPRINTS ARE COMPATIBLE TO 8 MSOP. 0.0-0.05
Doc. No. 3010, Rev. H
14
0.25
CAT1026, CAT1027
TDFN 3X3 PACKAGE (RD4)
8 5 A B 0.75 + 0.05
3.00 + 0.10 (S)
2X 0.15 C
1 3.00 + 0.10 (S) PIN 1 INDEX AREA
4
2X 0.15 C
0.0 - 0.05 8
5
0.75 + 0.05
1.50 + 0.10
2.30 + 0.10
C 0.25 min.
C0.35
PIN 1 ID
1 0.30 + 0.07 (8x) 1.95 REF. (2x) NOTE: 1. ALL DIMENSION ARE IN mm. ANGLES IN DEGREES. 2. COPLANARITY SHALL NOT EXCEED 0.08 mm. 3. WARPAGE SHALL NOT EXCEED 0.10 mm. 4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC(S) 5. REFER JEDEC MO-229 / WEEC
0.30 + 0.10 (8x)
0.65 TYP. (6x)
15
Doc No. 3010, Rev. H
CAT1026, CAT1027
Ordering Information
Prefix CAT Device # 1026 Suffix S I -30
TE13
Optional Company ID
Product Number 1026: 2K 1027: 2K
Temperature Range I = Industrial (-40C to 85C) E = Extended (-40C to +125C)
Tape & Reel SOIC: 2000/Reel TSSOP: 2000/Reel MSOP: 2500/Reel
Package P: PDIP S: SOIC R: MSOP U: TSSOP RD2: 8-pad TDFN (3x4.9mm, MSOP Footprint) RD4: 8-pad TDFN (3x3mm) L: PDIP (Lead free, Halogen free) V: SOIC (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) Z: MSOP (Lead free, Halogen free) ZD2: TDFN 3x4.9mm (Lead free, Halogen free) ZD4: TDFN 3x3mm (Lead free, Halogen free)
Reset Threshold Voltage 45: 4.5-4.75V 42: 4.25-4.5V 30: 3.0-3.15V 28: 2.85-3.0V 25: 2.55-2.7V
Note: (1) The device used in the above example is a CAT1026SI-30TE13 (Supervisory circuit with I2C serial 2k CMOS EEPROM, SOIC, Industrial Temperature, 3.0-3.15V Reset Threshold Voltage, Tape and Reel).
Doc. No. 3010, Rev. H
16
REVISION HISTORY
Date 9/25/2003 Rev. F Reason Added Green Package logo Updated DC Operating Characteristic notes Updated Reliability Characteristics notes 11/7/2003 G Eliminated Automotive temperature range Updated Ordering Information with "Green" package marking codes 4/12/2004 H Eliminated data sheet designation Updated Reel Ordering Information
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DPP TM AE2 TM I2C is a trademark of Philips Corporation. Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.
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Publication #: Revison: Issue date:
3010 H 4/12/04

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